1. Field of the Invention
The invention relates to data processing systems, in general, and, more particularly, to microprogrammable processors, and memory addressing in such systems.
2. Description of the Prior Art
Microprogrammable processors are well-known in the prior art. Data flow in such processors is controlled by gating circuits which are enabled by selective control signals. The central processor operates by means of control signals which are formed from microprogram words.
A sequence of microprogram words (or a "microprogram") defines a sequence of "micro operations" which specify the data transfer paths in the system, therefore defining the overall internal operation of the processor. The exact sequence of microprogram words may, typically, be established by the address portion in each microprogram word. Likewise, the address portion in each microprogram word may be the address in the control store which contains the next microprogram word to be used in sequence. The central processor unit (CPU) control alters the addresses based upon various internal and external conditions.
The central processor unit responds to machine language instructions. Each machine language instruction has an operation code and may have an operand address. In order to execute the instruction, the central processor unit must perform a series of internal data transfers. For example, the contents of a register known as the program counter must be applied to the memory bus so that the next instruction can be fetched. The operation code of the instruction must be applied to an instruction decoder in order to be decoded. The operands, identified by the operand addresses, must be transferred to the central processor unit for processing.
There are basically two ways of controlling internal data transfers--either through hardware (digital circuits) or firmware (microprogramming). There are advantages for each of the two ways. That is, the hardware techniques are generally faster, while firmware is more flexible. Although many simple, controlled data transfers can be performed by either hardware or firmware, once one technique is selected in prior art data processing systems, it is generally not possible to perform that data transfer using a different technique without redesigning the computer architecture. Thus, many controlled data transfers are performed in a microprogrammable processor by firmware, even though it might have been desired to perform that particular data transfer by hardware. Such disadvantages of microprogrammable processors are overcome by the present invention.
Although microprogrammable processors are the most relevant field of prior art, various hardware related techniques of address calculation are found in non-microprogrammable processors, especially in microprocessors. Reference is made to U.S. Pat. No. 4,202,035 which describes a hardware apparatus for generating addresses for use in a microprocessor. The referenced patent describes the use of an adder for adding at least a portion of the digital values of the data contained in first and second registers so that the resulting digital value is within the range of addresses of the addressable memory. However, the referenced patent does not contemplate the use of an adder which performs a calculation in which the resulting digital value may be beyond the capacity of the adder. This situation is increasingly probable with the development of microcomputer systems with greater memory addressing capability.